个人简介
代表论著
祁亮，上海交通大学微纳电子学系副教授、博士生导师，入选第八届中国科协青年托举计划，上海市浦江人才计划，科研领域包括高性能模数转换器、无线收发机及生物医疗电子。相关的研究成果在国际会议和期刊上发表超过30篇学术论文，包括6x ISSCC/ISSCC-SRP/VLSI/CICC, 2x JSSC, 5x TCASI/II, 等。
祁亮于2019年在澳门大学取得博士学位。2016-2017年在德国乌尔姆大学交流访问。博士毕业后曾在华为海思无线射频部工作，从事模拟集成电路设计，于2020年8月加入上海交通大学微纳电子学系。
祁亮博士目前主持国家重点研发计划港澳台专项，国家自然科学基金，华为海思联合研发等项目。他曾获得2021年度IEEE ASICON 杰出青年学者论文奖；2021、2022年度全国大学生集成电路创新大赛优秀指导教师称号； 2016年度澳门特别行政区研究生科技研发奖。
祁亮博士目前担任IEEE Transactions on Circuits and Systems II (IF=3.3)的副编辑，并担任IEEE APCCAS, ICSICT, ICTA及ASICON等多个会议TPC成员。
6x ISSCC/ISSCC-SRP/VLSI/CICC, 2x JSSC, 5x TCASI/II, 5x ISCAS.
期刊论文（Journal Papers）：
[J1] Liang Qi, A. Jain, D. Jiang, S.-W. Sin, R. P. Martins and M. Ortmanns, “A 76.6dB-SNDR 50MHz-BW 29.2mW Multibit CT Sturdy MASH ΔΣ Modulator with DAC Non-linearity Tolerance”, in IEEE Journal of Solid-State Circuits, Vol. 55, No. 2, pp. 344-355, Feb. 2020.
[J2] Liang Qi, S.-W. Sin, S.-P. U, R. P. Martins and F. Maloberti, “A 4.2mW 77.1dB-SNDR 5MHz-BW DT 2-1 MASH ΔΣ Modulator with Multirate Opamp Sharing”, in IEEE Transactions on Circuits and Systems I – Regular Papers, Vol. 64, No. 10, pp. 2641-2654, Oct. 2017.
[J3] Liang Qi, Y. Liu, S.-W. Sin, X. Xing, G. Wang, M. Ortmanns and R. P. Martins, “Wideband Continuous-time MASH Delta-Sigma Modulators: A Tutorial Review, in IEEE Transactions on Circuits and Systems II: Express, Early Access, 2022.
[J4] Liang Qi, S.-W. Sin, S.-P. U and R. P. Martins, “Resolution-enhanced sturdy MASH delta–sigma modulator for wideband applications”, in IET, Electronics Letters, Vol. 51, No. 14, pp. 1061–1063, Jul. 2015.
[J5] D. Jiang, Liang Qi, S.-W. Sin, F. Maloberti, and R. P. Martins, “A Time-Interleaved 2nd-Order ΔΣ Modulator Achieving 5-MHz Bandwidth and 86.1-dB SNDR Using Digital Feed-Forward Extrapolation”, in IEEE Journal of Solid-State Circuits, vol. 56, no. 8, pp. 2375-2387, Aug. 2021.
[J6] A. R. Mohamed, Liang Qi, Y. Li and G. Wang, “A Generic Nano-Watt Power Fully Tunable 1-D Gaussian Kernel Circuit for Artificial Neural Network”, in IEEE Transactions on Circuits and Systems II, Vol. 67, No. 9, pp. 1529-1533, Sep. 2020.
[J7] A. R. Mohamed, Liang Qi and G. Wang, “A Power-Efficient and Re-Configurable Analog Artificial Neural Network Classifier,” in Microelectronics Journal, vol. 111, pp. 1-10, May 2021.
[J8] C. Wang, Y. Ji, C. Ma, Q. Cai, Liang Qi and Y. Li, “An Ultra-Low-Voltage Level Shifter with Embedded Re-Configurable Logic and Time-Borrowing Latch Technique”, in IEEE Access, Vol. 9, pp. 79904-79910, May 2021.
[J9] D. Jiang, S.-W. Sin, Liang Qi, G. Wang and R. P. Martins, “Recent Advances in High-Resolution Hybrid Discrete-Time Noise-Shaping ADCs”, in IEEE Open Journal of the Solid-State Circuits Society, vol. 1, pp. 129-139, Oct. 2021.
[J10] J. Huang, T. Zhou, H. Liu, Liang Qi, Y. Liu and Y. Li, "Low Noise, High Linearity Sine Wave Generation Using Noise-Shaping Phase-Switching Technique," in IEEE Transactions on Instrumentation and Measurement, doi: 10.1109/TIM.2021.3139662.
[J11] H. Liu，T. Guo; P. Yan, Liang Qi, Mingyi Chen, G. Wang, Y. Liu, "A Hybrid 1st/2nd-order VCO-based CTDSM with Rail-to-Rail Artifact Tolerance for Bidirectional Neural Interface," in IEEE Transactions on Circuits and Systems II: Express Briefs, doi: 10.1109/TCSII.2022.3153786.
[J12] M Guo, S.-W. Sin, Liang Qi, D. Xu, G. Wang, R.P. Martins, “Background Timing Mismatch Calibration Techniques in High-Speed Time-Interleaved ADCs: A Tutorial Review, in IEEE Transactions on Circuits and Systems II: Express, Early Access, 2022.
会议论文(Conference Papers)：
[C1] Liang Qi, A. Jain, et al, “A 76.6dB-SNDR 50MHz-BW 29.2mW Noise Coupling Assisted CT Sturdy MASH ΔΣ Modulator with 1.5b/4b Quantizers in 28nm CMOS”, IEEE International Solid-State Circuits Conference (ISSCC), Feb. 2019.
[C2] Liang Qi, S.-W. Sin and R. P. Martins, “Multibit sturdy MASH delta-sigma modulator with error-shaped segmented DACs for wideband low-power applications”, IEEE International Conference on ASIC (ASICON), Oct. 2019. (会议优秀论文)
[C3] Liang Qi*, X. Qin, S.-W. Sin, C. Chen, F. Ye, and G. Wang, “Advances in Continuous-time MASH ΔΣ Modulators”, IEEE International Conference on ASIC (ASICON), Nov. 2021. (会议优秀青年学者论文奖)
[C4] Liang Qi, S.-W. Sin, S.-P. U, R. P. Martins and F. Maloberti, “A 12.5-ENOB 5MHz BW 4.2mW DT Multirate 2-1 MASH ΔΣ Modulator with Horizontal/Vertical Opamp Sharing in 65nm CMOS”, IEEE International Solid-State Circuits Conference (ISSCC) Student Research Preview, Feb. 2016.
[C5] D. Jiang, Liang Qi, S.-W. Sin, F. Maloberti, and R. P. Martins, “A 5MHz-BW, 86.1dB-SNDR 4X Time-Interleaved 2nd-order ΔΣ Modulator with Digital Feedforward Extrapolation in 28nm CMOS”, IEEE Symposium on VLSI Circuits, Jun. 2020.
[C6] G. Tan, H. Lu, X. Qin, J. Zhang, J. Zhang, Y. Liu and Liang Qi*, “A Self-coupled DT MASH ΔΣ Modulator with High Tolerance to Noise Leakage”, IEEE Asia Pacific Conference on Circuits and Systems (APCCAS), pp. 90-93, Dec. 2020.
[C7] X. Qin, J Zhang, Liang Qi*, S.-W. Sin, R. P. Martins and G. Wang, Discrete-Time MASH Delta-Sigma Modulator with Second-Order Digital Noise Coupling for Wideband High-Resolution Applications, IEEE International Symposium on Circuits and Systems (ISCAS), pp. 1-5, May 2021.
[C8] J. Zhang, G. Tan, Y. Hu, J. Zhao, M. Chen, Y. Li and Liang Qi*, A Multi-Rate Hybrid DT/CT MASH ΔΣ Modulator with High Tolerance to Noise Leakage, IEEE International Symposium on Circuits and Systems (ISCAS), pp. 1-5, May 2021.
[C9] Y. Luo, Liang Qi, A. Jain and M. Ortmanns, “A High-Resolution ΔΣ D/A Converter Architecture with High Tolerance to DAC Mismatch”, IEEE International Symposium on Circuits and Systems (ISCAS), May 2018.
[C10] D. Jiang, Liang Qi, S.-W. Sin, F. Maloberti and R. P. Martins, “A 5MHz-BW, 86dB-SNDR 4X Time-Interleaved 2nd-order ΔΣ Modulator with Digital Feedforward Extrapolation in 28nm CMOS,” IEEE International Solid-State Circuits Conference (ISSCC) Student Research Preview, Feb. 2020.
[C11] A. R. Mohamed, Liang Qi, G. Tan, and G. Wang, “A Power-Efficient and Re-Configurable Mixed-Mode Artificial Neural Network Classifier,” International Solid-State Circuits Conference Student Research Preview, San Francisco, CA, USA, Feb. 2021. (ISSCC学生科研展望单元优秀海报奖)
[C12] W. Chen, M. Chen, Y. Hao, Liang Qi and J. Zhao, "A 1-μA-quiescent-current Capacitor-less LDO Regulator with Adaptive Embedded Slew-Rate Enhancement Circuit," IEEE International Symposium on Circuits and Systems (ISCAS), pp. 1-5, May 2021.
[C13] C. Ma, Y. Ji, Q. Cai, T. Zhou, Liang Qi and Y. Li, "An Energy-Efficient Level Shifter Using Time Borrowing Technique for Ultra Wide Voltage Conversion from Sub-200mV to 3.0V," IEEE International Symposium on Circuits and Systems (ISCAS), pp. 1-5, May 2021.
[C14] J. Zhang, Y. Zhao, M. Chen, C. Chen, F. Ye and Liang Qi*,"Self-coupled MASH Delta-Sigma Modulator with Zero Optimization," IEEE International SoC Design Conference (ISOCC), Oct. 2021.
[C15] Liang Qi*, T. Ni, X. Qin, M. Chen, Y. Li and G. Wang, " Continuous-time Delta-Sigma Modulators: Single-loop versus MASH," IEEE International SoC Design Conference (ISOCC), Oct. 2021.
[C16] D. Zhan, C. Chen, Liang Qi, F. Ye and J. Ren, " Machine Learning based Prior-Knowledge-Free Nyquist ADC Characterization and Calibration," IEEE International SoC Design Conference (ISOCC), Oct. 2021.
[C17] Y. Hu, J. Zhang, Y. Zhao, M. Chen and Liang Qi*, “Discrete-Time MASH Delta-Sigma Modulator with an IIR-based Self-Coupling”, IEEE International Conference on Integrated Circuits, Technologies and Applications (ICTA), Nov. 2021.
